Among manufacturing processes of modern very-large-scale integrated circuits (VLSIs), a lithography process is one of the important steps. Lithography is an important mean to transfer design patterns of an integrated circuit (IC) from a mask onto a silicon slice by a lithography machine. When the design patterns of the IC on the mask is imaged on the silicon slice via a projection objective lens of the lithography machine, light diffraction becomes more significant as characteristic sizes of the design patterns on the mask become smaller.
After rule-based optical proximity correction (OPC) and model-based optical proximity effects correction, a mask design optimization technique can be based on inversion lithography technology (ILT). The ILT aims at realizing patterns on the silicon slice (or wafer), by obtaining an ideal mask design pattern (typically as grayscale patterns or so-called pixel-based mask patterns) through complicated inversion mathematical calculations, then obtaining a final polygon-based mask design pattern through simplification and extraction operations.
Existing ILT mask optimizations can have high time cost, due to hundreds of optimization iterations and application of an OPC model to simulate a silicon wafer image for current mask optimization results for each optimization. Typically, more than 10 hours (300 CPU cores) are needed to optimize design patterns of hundreds of square microns. For a full chip (e.g., 22 mm*32 mm), it can take months and the computation load can be heavy.